The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a semiconductor device having a bulb-shaped recess gate.
In a conventional method for forming a planar gate interconnection line, a gate is formed over a flat active region. The current demand for large scale integration of semiconductor devices has caused a decrease in channel length and an increase in implantation doping concentration. A junction leakage is often generated due to an increased electric field. Thus, it becomes difficult to secure a satisfactory refresh property of a device. Furthermore, a channel length and a channel width are restricted, and electron mobility is reduced due to the increased channel doping concentration. As a result, it is desired to secure a sufficient channel current.
FIGS. 1A and 1B are cross-sectional views illustrating a conventional method for fabricating a semiconductor device having bulb-shaped recess gates. As shown in FIG. 1A, a pad oxide layer 12 and a hard mask 13, each exposing regions where recesses are to be formed, are formed over a substrate 11. The substrate 11 is etched using the hard mask 13 as an etch mask to form a plurality of first recesses 14 having vertical profiles. While the first recesses 14 are formed, plasma damage A1 may be incurred on sidewalls of the first recesses 14 (i.e., junction regions).
As shown in FIG. 1B, the substrate 11 beneath the first recesses 14 is subjected to an isotropic etching process to form a plurality of second recesses 15 having round profiles. While the second recesses 15 are formed, plasma damage A2 may also be incurred on the junction regions.
FIG. 2 is a transmission electron micrograph (TEM) illustrating a semiconductor device having typical bulb-shaped recess gates. Given portions of a substrate are selectively subjected to a plasma etching process to form the semiconductor device having the bulb-shaped recess gates 100. The semiconductor device having the bulb-shaped recess gates 100 has an increased channel length such that a junction region may not shrink.
Since the bulb-shaped recess gates 100 are formed using a plasma dry etching process, plasma damage may be incurred twice. The plasma damage may degrade transistor quality. If polymers are deposited over lower portions of the recesses during the etching process, the bulb-shaped recess gates 100 may be formed at a size that is smaller than desired. Alternatively, the bulb-shaped recess gates 100 may not be formed at all.